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Innatera, the Dutch startup that makes neuromorphic AI accelerators for neural network spiking, produced its first chips, measured their performance and revealed details of their architecture.
The company also announced that Alberto Sangiovanni-Vincentelli, co-founder of Cadence and Synopsys, has joined the company as Chairman of the Board of Directors. The industry veteran is currently a professor at the University of California at Berkeley.
The Innatera chip is designed to speed up Spiking Neural Networks (SNNs), a type of neuromorphic AI algorithm based on brain biology that uses the timing of spikes in an electrical signal to perform pattern recognition tasks. SNNs are completely different in structure from mainstream AI algorithms and therefore require dedicated hardware for acceleration, but typically offer significant power consumption and latency benefits for sensor edge applications.
Most other companies working on neural network algorithms and hardware (e.g. Prophesee) target images and video streams. Innatera has decided to focus on audio (sound and speech recognition), health (vital signs monitoring) and radar (for consumer / IoT use cases like fall sensors for the elderly protecting privacy).
“These sensors have time series data instead of images that are very parallel,” said Marco Jacobs, Innatera VP Marketing and Business Development, in an interview with EE times. “Our array is particularly good at processing time series data … it goes well with the technology. From a market perspective, too, we see many interesting applications in this area and not so many solutions that deal with it. “
Another common feature of these three applications is that the performance range is very narrow, since processing in the sensor node is required. In Innatera’s tests, each spike event (each neuron that fires in response to input data) consumed less than one picoJoule of energy – actually less than 200 FemtoJoule in TSMC 28 nm, confirmed Innatera. This approaches the amount of energy used by biological neurons and synapses. A typical audio keyword spotting application required fewer than 500 spikes per inference, resulting in “low sub-milliwatt power dissipation,” according to Innatera CEO Sumeet Kumar. In this case, clusters of neurons firing together represent different phonemes in the language.
Innatera’s neural spiking processor uses a parallel array of spiking neurons and synapses to accelerate continuous-time SNNs with fine-grained temporal dynamics. The device is an analog / mixed-signal accelerator that was developed to take advantage of SNN’s ability to incorporate the concept of time into the processing of the data.
One of the key aspects of Innatera’s compute fabrics is their programmability, which is important for two reasons.
First the programming of various SNNs on the chip. Neurons need to be flexibly connected – the brain uses very complex neural network topologies to get things done efficiently, which requires complex connections between neurons that need to be modeled in silicon.
Second, to optimize performance. Instead of presenting information as bits in words, information in an SNN is presented as precisely timed peaks. The timing of the tips has to be manipulated on a very fine-grained level in order to gain insight into the data. The neurons and the connections between them (the synapses) must therefore exhibit complex timing behavior. These behaviors can be customized through the Innatera SDK to optimize performance.
Innatera describes its chip as an analog mixed signal or “digitally assisted analog”. Neurons and synapses are implemented in analog silicon to maintain extremely low power consumption. Analog electronics also enable time-continuous networks (digital electronics would require discretization). This is important for SNNs because by their very nature they must have an idea of time and be able to maintain certain states over a period of time.
“This is much easier in the analog domain – you don’t have to shift the complexity of health acquisition to the network topology,” said Kumar. “Our computing elements naturally retain this status information. That is the reason why we do things in the analog field. “
Minor inconsistencies in manufacturing between computing elements on the chip and between different chips can be a problem for the accurate implementation of neural networks in the analog domain. Innatera’s solution is to group neurons into so-called segments that are carefully designed to match the path lengths and the number of neurons.
The segment design “essentially allows us to use the best of analog circuitry while minimizing those non-idealities that you would normally have in an analog circuit,” said Kumar. “All of this was essentially done to ensure that neurons within a segment exhibit deterministic behavior and function similarly to their immediate neighbors.”
Inconsistencies between different chips can lead to problems when the same trained network is rolled out to devices in the field. Innatera deals with this with software.
“Mismatch and variability are covered deeply in the SDK,” said Kumar. “If you’re a power user, we can show you some of it, but a typical programmer doesn’t have to worry about it.”
Innatera, a spin-out from Delft University of Technology, was already working with revenue customers on its SNN algorithms before jumping into hardware and starting a € 5 million (around $ 6 million) seed round towards the end of 2020.
“We have worked with a number of clients since we actually started the company, and those commitments are ongoing – they have matured a lot,” said Kumar. “We hope to be able to show more demonstrations with some of these customers later this year.”
Kumar said the company will maintain its focus as a computing solutions company, which means it will deliver turnkey solutions that include both hardware and application-specific SNN algorithms.
Innatera’s first chip is suitable for audio, health and radar applications. The company’s roadmap could include further optimized chips for each of the applications.
“We designed the device so that we can accelerate a variety of sharp neural networks,” said Kumar. “[Our chip] can implement these networks across application domains. However, as we get deeper into the domains it may be necessary to tweak the hardware design, and this is what we will look at in the future. Right now the hardware is not overly specialized in any particular class of application or any type of spiking neural network, the goal is to support a wide variety of them in general within the architecture. “
Samples of the first chip should be available before the end of 2021.